The present invention relates generally to content addressable memory (CAM) devices.
A content addressable memory (CAM) device is a storage device that can be instructed to compare a specific pattern of comparand data with data stored in its associative CAM array. The entire CAM array, or segments thereof, is searched in parallel for a match with the comparand data. If a match exists, the CAM device indicates the match by asserting a match flag. Multiple matches may also be indicated by asserting a multiple match flag. The CAM device typically includes a priority encoder to translate the highest priority matching location into a match address or CAM index.
When the CAM array is segmented into many CAM array blocks, the priority encoder may also be distributed or segmented such that each block has its own encoder. The outputs of the encoders can then be combined to generate the address of the highest priority matching location. This approach, however, may use a significant amount of die area in an integrated circuit to implement the distributed priority encoder. Other approaches have suggested a hierarchical priority encoding scheme that includes a main priority encoder and a subblock priority encoder. The subblock priority encoder monitors the match signals from the individual blocks and sequentially enables each block to provide its match results to the main priority encoder. This approach may require a significant amount of time to reach the block having the highest priority matching entry.
A method and apparatus for determining the address of a highest priority matching entry in a segmented content addressable memory device is disclosed. For one embodiment, a segmented CAM device is disclosed that includes m CAM array blocks each having n rows of CAM cells coupled to one of n corresponding match lines. The CAM array blocks have a predetermined priority based on their addresses such that the first CAM array block has the highest priority addresses and the mth CAM array block has the lowest priority addresses. Comparand data is provided for comparison with entries in each of the CAM array blocks. Each row of CAM cells in each block has arrow enable logic circuit. A main priority encoder is coupled to the row enable logic circuits of the mth CAM array block. Each CAM array block also has an associated match flag circuit to determine a match flag signal for the block. A block priority encoder encodes the match flag signals into a block address of the highest priority matching location. The block address is provided to a decoder that decodes the block address. The decoded block address enables one of the groups of row enable logic circuits associated with the CAM array block having the highest priority matching location to provide its match results to the main priority encoder. The main priority encoder determines the subblock address of the matching entry in that CAM array block. The block address and the subblock address form the address of the highest priority matching entry or location in the entire CAM array.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.